1. Field of the Invention
The present invention relates to an analog front end circuit and the method thereof, especially when an analog front end circuit is processed in the manner of sampling twice and the method thereof.
2. Description of the Prior Art
The analog front end circuit (AFE circuit) is quite an important element in an image capture device (e.g. digital still camera and digital video camera). The analog front end circuit is mainly used for receiving the output signals of the image sensor and converting the pixel signals to digital signals for subsequent elements to process.
The output signal of the image sensor (e.g. Charged-Coupled devices, CCD) is converted to digital signal via signal modulation and analog-to-digital converter (ADC) for subsequent processing. Please refer to FIG. 1. FIG. 1 is a schematic diagram of an image capture device of the prior art. The image capture device 2 of the prior art utilizes an optical system 4 to capture the optical image and performs signal processing via a CCD sensor 6, an AFE circuit 8, and a digital processor 9 subsequently.
The function of the AFE circuit 8 is to convert the CCD signal 10 outputted by the CCD sensor 6 to a digital signal 7 via ADC and output the digital signal 7 to the digital processor 9.
Please refer to FIG. 1 and FIG. 2. FIG. 2 is a schematic diagram of a sample and hold circuit 20 of the AFE circuit 8 of the prior art. The sample and hold circuit 20 of the AFE circuit 8 of the prior art comprises an operational amplifier 22, a set of capacitors 24, 26, a sample switch 28, and a hold switch 30. The sample and hold circuit 20 is used for sampling and holding the CCD signal 10 and outputting an output signal 42, wherein the sample switch 28 is controlled by a sample pulse signal (not shown in FIG. 2), and the hold switch 30 is controlled by a hold pulse signal (not shown in FIG. 2).
Please refer to FIG. 3. FIG. 3 is a time sequence diagram of the CCD signal 10, the sample pulse signal 32, and the hold pulse signal 34 of the prior art. In the time sequence diagram of FIG. 3, the horizontal axis represents time, and the vertical axis represents amplitude of signal. The CCD signal 10 is a periodic analog signal with period of T. The CCD signal 10 of each cycle comprises a reset signal 14, a first reference voltage signal 16, and a first voltage level signal 18. The sample pulse signal 32 comprises a plurality of square waves 36. Each square wave 36 comprises a positive edge 38 and a negative edge 40, wherein the positive edge 38 of the square wave 36 will set off the sample switch 28 to be a close state, and the negative edge 40 will set off the sample switch 28 to be an open state. The hold pulse signal 34 comprises a plurality of square waves 36. Each square wave 36 comprises a positive edge 38 and a negative edge 40, wherein the positive edge 38 of the square wave 36 will set off the hold switch 30 to be the close state, and the negative edge 40 will set off the hold switch 30 to be the open state.
Please refer to FIG. 2 and FIG. 3. When the first reference voltage signal 16 is inputted to the sample and hold circuit 20, the sample switch 28 and the hold switch 30 are in the close state. Therefore, the voltage value of the first reference voltage signal 16 is sampled to the capacitor 24. When the first voltage level signal 18 is inputted to the sample and hold circuit 20, the sample switch 28 is in the close state while the hold switch 30 is in the open state. As a result, the sample and hold circuit 20 outputs an output signal 42, which is a difference D multiplied by a gain value Gp (not shown). The difference D is a voltage difference between the first reference voltage signal 16 and the first voltage level signal 18. The gain value Gp is calculated by the following equation:Gp=Ca/Cb 
Wherein Ca is a capacitance value of the capacitor 24, Cb is a capacitance value of the capacitor 26.
However, due to the characteristics variety of electronic parts, the reset signal 14, the first reference voltage signal 16, and the first voltage level signal 18 of the CCD signal 10 all comprise a transition state 44 and a steady state 46. Therefore, only the steady state 46 from the first reference voltage signal 16 and the first voltage level signal 18 may be sampled. The width W of the square wave within the sample pulse signal 32 and the hold pulse signal 34, which enables the sample switch 28 and the hold switch 30 to be at the close state, is usually half of width P of the reference voltage signal 16 or the second voltage level signal 18. The above condition usually causes needing a higher bandwidth of the operational amplifier 22. Hence, choosing a operational amplifier 22 with a higher bandwidth is necessary for sampling and holding the CCD signal 10 accurately.
Besides, the CCD signal 10 is inputted into the operational amplifier 22 within the sample and hold circuit 20 of the prior art via a single end. If the CCD signal 10 is affected by noise, environmental temperature changes, or characteristics variety of electronic parts, an error may occur in the voltage level of the first reference voltage signal 16, thus leading to an error in the output signal 42 outputted by the sample and hold circuit. Furthermore, the sample and hold circuit 20 of the CCD signal 10 of the prior art cannot process or compensate the error.